METHOD FOR AUTOMATICALLY SYNTHESIZING LOGIC CIRCUIT

摘要

PROBLEM TO BE SOLVED: To satisfy a request for designing a semiconductor LSI operating at a high speed, and a request for deigning the semiconductor LSI in a short period, and to automatically synthesize logic circuits. SOLUTION: The logic circuits are experimentally automatically synthesized and representative wiring length is estimated at every fan out based on a net list obtained as a result (p22). Representative wiring length is set to be center wiring length WLmed(fn) on plural wirings. The standard deviationσmed(fn) of plural wirings and a probability coefficient K(fn) being the coefficient are operated for the respective fan outs fn based on the net list. Decided wiring length WL(fn) for every fan out fn are calculated by an operation expression WL(fn)=WLmed(fn)+K(fn).σmed(fn) (p23). The probability coefficient K(fn) is set to be a small value or a large value in accordance with the request of deign. The logic circuits are automatically synthesized by using a virtual wiring model containing decided wiring length WL(fn) and the layout of the logic circuit is generated based on the net list obtained as the result.