| 摘要 |
A ferroelectric memory device includes: a first p-channel type MISFET connected between a first bit line and a first node; a second p-channel type MISFET connected between a second bit line and a second node; a first negative potential generation circuit connected to the first node; and a second negative potential generation circuit connected to the second node, wherein a gate terminal of the first p-channel type MISFET and the second node are connected to each other, and a gate terminal of the second p-channel type MISFET and the first node are connected to each other.
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