发明名称 |
Integrated memory controller |
摘要 |
A circuit for reading data from a buffer memory, which is Synchronous Dynamic Random access Memory ("SDRAM"), or Double Data Rate-Synchronous Dynamic Random Access Memory ("DDR") comprises logic for managing programmable clock signal relationships such that data that is read from the DDR is centered within a DQS signal which is generated from the DDR and then appropriately delayed.
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申请公布号 |
US7596053(B1) |
申请公布日期 |
2009.09.29 |
申请号 |
US20060542726 |
申请日期 |
2006.10.04 |
申请人 |
MARVELL INTERNATIONAL LTD. |
发明人 |
WHITE THEODORE C.;JAYABHARATHI DINESH |
分类号 |
G11C11/00;G06F13/16;G11C8/00 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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