| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a register controlled delay locked loop capable of minimizing a delay locked time. <P>SOLUTION: This register controlled delay locked loop is equipped with a phase comparing means which generates a delay increasing signal and a delay decreasing signal by comparing a feedback clock with a reference signal, a shift register control means which generates a shift control signal according to these signals and a shift register which decides an amount of delay according to the shift control signal. The shift register is equipped with a latch which is initialized by a reset signal and is equipped with positive and negative output stages, a delay selection signal generating part which generates a delay selection signal according to the latch value of a prescribed stage and a preceding stage and a switching part which provides first and second discharge paths for discharging the positive and negative output stages of a latch according to a high-speed shift left control signal and a normal shift right control signal and latch values of adjacent stages in every stage and the first discharge path is equipped with a pair of switching elements which are controlled by a normal shift left control signal for every stages of a fixed number. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
