A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit- parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.
申请公布号
WO2016133611(A1)
申请公布日期
2016.08.25
申请号
WO2016US13174
申请日期
2016.01.13
申请人
MICRON TECHNOLOGY, INC.
发明人
KARDA, Kamal M.;TAO, Qian;RAMASWAMY, Durai Vishak Nirmal;LIU, Haitao;PRALL, Kirk D.;CHAVAN, Ashonita A.