发明名称 |
COMPUTER-SYSTEM |
摘要 |
PURPOSE: To incorporate parallel array processors on a single semiconductor silicon chip. CONSTITUTION: The parallel array processors for large scaled parallel application are formed by low output CMOS provided with a DRAM processing mechanism and processing elements are incorporated on a single chip. The eight processors on the single chip have the processing elements connected to themselves, large scaled memories and input/output mechanisms and they are connected by a corrected topology based on a hypercube. Nodes are connected by a hypercube network topology, a corrected hypercube network topology, a ring network topology or an intra-ring network topology. A programmable router for route-designating data and control information between memory processor memories and between computer system nodes is provided. |
申请公布号 |
JPH0635872(A) |
申请公布日期 |
1994.02.10 |
申请号 |
JP19930109314 |
申请日期 |
1993.05.11 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
KURAIBU ARAN KORINZU;MAIKERU CHIYAARUZU DATSUPU;JIEEMUZU UOREN DEIIFUENDERUFUAA;DEIBUITSUDO KURISUTOFUAA KUCHINSUKI;BIRII JIYATSUKU NOURUZU;RICHIYAADO EDOWAADO NIIYA;ERITSUKU YUUJIN RETAA;ROBAATO RIISUTO RICHIYAADOSON;DEIBUITSUDO BURUUSU RORUFU;BUINSENTO JIYON SUMOORARU |
分类号 |
F02B75/02;G06F15/173;G06F15/80 |
主分类号 |
F02B75/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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