发明名称 |
Integrated semiconductor memory circuit and a method for operating the same |
摘要 |
The invention relates to an integrated semiconductor memory, in particular a DRAM memory, in which primary sense amplifiers (SA) are coupled to a bit line (BL) of a respective cell block and can be connected to a common local data line (LDQ) by means of a respective assigned CSL switch in response to a CSL signal and in which an MDQ/LDQ switch arrangement connects a main data line (MDQ) to the local data line (LDQ) of a respective cell block in response to an MDQ/LDQ switch signal. In the case of the semiconductor memory, a control input of each CSL switch is connected to an AND element, which ANDs the CSL signal with the MDQ/LDQ switch signal and thereby activates the CSL switches only in cell blocks in which a word line has been activated.
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申请公布号 |
US2004184333(A1) |
申请公布日期 |
2004.09.23 |
申请号 |
US20030742761 |
申请日期 |
2003.12.23 |
申请人 |
PROELL MANFRED;SCHROEDER STEPHAN;SCHNEIDER RALF;KLIEWER JOERG |
发明人 |
PROELL MANFRED;SCHROEDER STEPHAN;SCHNEIDER RALF;KLIEWER JOERG |
分类号 |
G11C7/10;G11C11/4096;G11C11/4097;(IPC1-7):G11C7/02 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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