| 摘要 |
PROBLEM TO BE SOLVED: To improve timing analysis accuracy and improve timing analysis efficiency. SOLUTION: With a circuit analysis of divided block units, simulation information is saved about each block (100). Paths that must be analyzed are recognized (200). About the paths that must be analyzed, the divided blocks are coupled with the use of results of a static timing analysis and the block-specific simulation conditions to generate a SPICE deck (600). Simulation results from the generated SPICE deck are reflected in the static timing analysis (300). COPYRIGHT: (C)2008,JPO&INPIT
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