Method and apparatus for hardware-accelerated encryption/decryption

摘要

An integrated circuit for data encryption/decryption and secure key management is disclosed. The integrated circuit may be used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems. An embodiment of the integrated circuit includes a run-time scalable block cipher circuit, wherein the run-time scalable block cipher circuit is run-time scalable to balance throughput with power consumption.

主权项

1. An apparatus comprising:
a key-based block cipher circuit, the block cipher circuit configured to encrypt a data block based on a key; wherein the block cipher circuit comprises a plurality of round circuits that are arranged in a pipelined sequence of operatively adjacent round circuits, the round circuits for simultaneously performing rounds of encryption; and wherein the block cipher circuit is run-time scalable with respect to how many of the round circuits are active and how many passes through the round circuits are needed to encrypt a data block, and wherein the run-time scalability is achieved via a member of the group consisting of (1) clock enable propagation where a clock enable signal is propagated through the pipelined sequence along with data blocks to control whether each round circuit is active or inactive, and (2) control over an output bus and a data feedback bus for the pipelined sequence via a plurality of tri-state buffers, where each tri-state buffer holds an output from a round circuit and where a power control circuit drives the tri-state buffers via an enable signal that operates to selectively connect and disconnect the tri-state buffers to and from the output bus and the data feedback bus.