Mixing of low speed and high speed clocks to improve test precision of a digital integrated circuit

摘要

Implementations of the present disclosure involve an apparatus and/or method for mixing high speed and low speed clock signals during structural testing of a digital integrated circuit to improve the test precision and efficiency. In particular, the apparatus and/or method allow for a testing device to perform stuck-bit testing of the circuit by releasing one or more clock cycles of a low speed clock signal. Further, without having to reset the testing of the circuit, at-speed testing of the circuit may be conducted by the testing device. In one embodiment, at-speed testing occurs by activating a mode signal associated with the circuit design that instructs one or more clock cycles from an internal clock signal to the circuit to be released. The testing device may return to stuck-bit testing at a low speed clock signal, or continue with at-speed testing using the high speed internal clock signal.

主权项

1. A method for testing of a microelectronic circuit comprising:
scanning in a test pattern into the microelectronic circuit through one or more inputs to the microelectronic circuit; transmitting one or more pulses of a first clock signal to the microelectronic circuit, the first clock signal being from a first clock source to the microelectronic circuit; prior to scanning out a final value of the transmitted one or more pulses of the first clock signal:
asserting a mode change signal associated with the microelectronic circuit, the mode change signal indicating a change in clocking logic applied to the microelectronic circuit;enabling a second clock signal to the microelectronic circuit, the second clock signal being from a second clock source to the microelectronic circuit, the second clock source different than the first clock source; andtransmitting one or more pulses of the second clock signal to the microelectronic circuit; andscanning out the final value and comparing the final value to an expected result.