Static random access memory

摘要

A static random access memory (SRAM) including at least a SRAM cell is provided. A gate layout of the SRAM cell includes first to fourth strip doped regions, a recessed gate line and first and second gate lines. The first to fourth strip doped regions are disposed in the substrate in order and separated from each other. The recessed gate line intersects the first to fourth strip doped regions. The first to fourth strip doped regions are disconnected at intersections with the recessed gate line. The first gate line intersects the first and the second strip doped regions. The first and the second strip doped regions are disconnected at intersections with the first gate line. The second gate line intersects the third the fourth strip doped regions. The third and the fourth strip dopeds region are disconnected at intersections with the second gate line.

主权项

1. A static random access memory, comprising at least one static random access memory cell, wherein a gate layout of the static random access memory cell comprises:
a first strip doped region, a second strip doped region, a third strip doped region, and a fourth strip doped region, disposed in a substrate in order and separated from each other; a recessed gate line, intersecting the first strip doped region, the second strip doped region, the third strip doped region, and the fourth strip doped region, wherein the first strip doped region, the second strip doped region, the third strip doped region, and the fourth strip doped region are disconnected at intersections with the recessed gate line; a first gate line, intersecting the first strip doped region and the second strip doped region, wherein the first strip doped region and the second strip doped region are disconnected at intersections with the first gate line; and a second gate line, intersecting the third strip doped region and the fourth strip doped region, wherein the third strip doped region and the fourth strip doped region are disconnected at intersections with the second gate line.