| 摘要 |
PURPOSE:To avoid a synchronization bit error detection circuit from being complicated due to identification of a location of a cyclic synchronization bit in the frame synchronization circuit of PCM communication. CONSTITUTION:Input PCM data are stored in a shift circuit 20, bits in intermediate taps 21-2m are compared by a synchronization pattern comparator circuit 30, and a synchronization pattern is detected by storing and selecting the result at a synchronization pattern detection circuit 40. A pulse generator 50 generates a periodic pulse, an error in input synchronization bits is discriminated at the timing and when in error, the error is corrected by an invereter 12 and a selector 13 and the result is inputted to a shift circuit 20 to prevent propagation of the error thereby eliminating the need of identifying the location of the error bit in the synchronization pattern. |
