发明名称 Structure and method to increase contact area in unmerged EPI integration for CMOS FinFETs
摘要 Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (CMOSFET) having unmerged epitaxial source/drain regions and methods for forming such source/drain contact structures are provided by forming wrap-around source/drain contact structures for both n-type FinFETs and p-type FinFETs. Each of first source/drain contact structures for the n-type FinFETs includes at least one first conductive plug encapsulating epitaxial first source/drain regions on one side of a gate structure, while each of second source/drain contact structures for the p-type FinFETs includes at least a contact metal layer portion encapsulating epitaxial second source/drain regions on one side of the gate structure, and a second conductive plug located over a top surface of the contact metal layer portion.
申请公布号 US9362285(B2) 申请公布日期 2016.06.07
申请号 US201414505000 申请日期 2014.10.02
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 Basker Veeraraghavan S.;Cheng Kangguo;Khakifirooz Ali
分类号 H01L29/78;H01L27/092;H01L21/8238;H01L21/225;H01L29/161;H01L23/528;H01L23/532 主分类号 H01L29/78
代理机构 Scully, Scott, Murphy & Presser, P.C. 代理人 Scully, Scott, Murphy & Presser, P.C. ;Meyers Steven J.
主权项 1. A semiconductor structure comprises: a plurality of first semiconductor fins located on a first region of a substrate, wherein each of the plurality of first semiconductor fins has a channel region disposed between a pair of first epitaxial source/drain regions, wherein adjacent first epitaxial source/drain regions are separated by a first gap; a plurality of second semiconductor fins located on a second region of the substrate, wherein each of the plurality of second semiconductor fins has a channel region disposed between a pair of second epitaxial source/drain regions, wherein adjacent epitaxial second source/drain regions are separated by a second gap; a gate structure overlying the channel portion of each of the plurality of first semiconductor fins and the plurality of second semiconductor fins; a pair of first source/drain contact structures electrically coupled to the first epitaxial source/drain regions located on either side of the gate structure, wherein each of the first source/drain contact structures comprises at least a first conductive plug encapsulating the first epitaxial source/drain regions on one side of the gate structure and in contact with all surfaces of the epitaxial first source/drain regions; and a pair of second source/drain contact structures electrically coupled to the second epitaxial source/drain regions located on either side of the gate structure, wherein each of the second source/drain contact structures comprises at least a contact metal layer portion encapsulating the second epitaxial source/drain regions on one side of the gate structure and in contact with all surfaces of the second epitaxial source/drain regions and a second conductive plug located on a top surface of the contact metal layer portion.
地址 Armonk NY US