Bitline regulator for high speed flash memory system

摘要

A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.

主权项

1. A memory system, comprising:
an array of memory cells organized into rows and columns, wherein each column of memory cells is coupled to a bit line; and a bitline regulator for applying a bias voltage to each bit line, the bitline regulator comprising:
a first circuit for outputting a plurality of trim bits; anda second circuit adjusting the bias voltage in response to the plurality of trim bits; wherein the first circuit comprises:
a sample and hold circuit for generating a sampled voltage based on the bias voltage;a comparator for comparing the sampled voltage to a reference voltage and generating an output; andan arbiter for receiving the output from the comparator and generating the trim bits.