发明名称 Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof
摘要 A dual-side exposed semiconductor package with ultra-thin die and a manufacturing method are disclosed. A die having a source electrode and a gate electrode at top surface is flipped and attached to a die paddle of a lead frame and then is encapsulated with a first molding compound. The first molding compound and the die are ground to reduce the thickness. A mask is applied atop the lead frame with the back of the flipped die exposed and a metal layer is deposited on the exposed area at the back of the flipped die. A metal clip is attached to the back of the flipped die. A second molding compound is deposited on the lead frame with the top surface of the metal clip exposed from the top surface of the second molding compound and the bottom surface of the lead frame exposed from the bottom surface of the second plastic molding compound.
申请公布号 US9437528(B1) 申请公布日期 2016.09.06
申请号 US201514862136 申请日期 2015.09.22
申请人 ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. 发明人 Gong Yuping;Sui Xiaoming;Xue Yan Yun;Lu Jun
分类号 H01L23/495;H01L21/78;H01L21/56;H01L23/31 主分类号 H01L23/495
代理机构 代理人 Lin Chen-Chi
主权项 1. A method for manufacturing dual-side exposed semiconductor packages with ultra-thin dies, the method comprising the steps of: preparing a plurality of dies, each of the plurality of dies having a source electrode and a gate electrode on a top surface of said each of the plurality of dies; providing a lead frame including a plurality of die paddles, said each of the plurality of dies being flipped and the top surface of said each of the plurality of flipped dies being attached to a respective die paddle of the plurality of die paddles; depositing a respective molding compound of a plurality of molding compounds on each of the plurality of flipped dies; grinding at top surfaces of the plurality of molding compounds so as to thin the plurality of molding compounds and to expose back surfaces of the plurality of flipped dies, and then grinding at top surfaces of the plurality of thinned molding compounds and the exposed back surfaces of the plurality of flipped dies so as to further thin the plurality of thinned molding compounds and the plurality of flipped dies; depositing a mask layer covering the lead frame and the plurality of further thinned molding compounds; depositing a respective back metal layer of a plurality of back metal layers on an exposed back surface of each of the plurality of further thinned flipped dies; removing the mask layer; attaching a respective metal clip of a plurality of metal clips to each of the plurality of back metal layers; depositing a molding compound layer covering the lead frame and surrounding the plurality of further thinned flipped dies so as to form a processed lead frame, top surfaces of the plurality of metal clips being exposed and a bottom surface of the lead frame being exposed; and singulating the dual-side exposed semiconductor packages from the processed lead frame.
地址 Sunnyvale CA US