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1. An integrated circuit comprising:
a first variable capacitor array comprising a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output, wherein a first variable capacitor cell of the plurality of variable capacitor cells comprises:
two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors electrically connected in a cascade between the RF input and the RF output, wherein a first pair of the two or more pairs of anti-series MOS capacitors comprises a first MOS capacitor and a second MOS capacitor electrically connected in anti-series, and wherein a second pair of the two or more pairs of anti-series MOS capacitors comprises a third MOS capacitor and a fourth MOS capacitor electrically connected in anti-series, wherein the first MOS capacitor comprises a gate that operates as an anode and a source and a drain electrically connected to one another to operate as a cathode, wherein the second MOS capacitor comprises a gate that operates as an anode and a source and a drain electrically connected to one another to operate as a cathode, wherein the third MOS capacitor comprises a gate that operates as an anode and a source and a drain electrically connected to one another to operate as a cathode, wherein the fourth MOS capacitor comprises a gate that operates as an anode and a source and a drain electrically connected to one another to operate as a cathode, wherein the anode of the first MOS capacitor is electrically connected to the anode of the second MOS capacitor, wherein the anode of the third MOS capacitor is electrically connected to the anode of the fourth MOS capacitor, and wherein the cathode of the second MOS capacitor is electrically connected to the cathode of the third MOS capacitor;a first control biasing resistor including a first end configured to receive a first bias voltage and a second end electrically connected to the anodes of the first and second MOS capacitors;a second control biasing resistor including a first end configured to receive the first bias voltage and a second end electrically connected to the anodes of the third and fourth MOS capacitors;a first DC biasing resistor including a first end electrically connected to a cathode of the first MOS capacitor and a second end electrically connected to a first voltage;a second DC biasing resistor including a first end electrically connected to the cathodes of the second and third MOS capacitors and a second end electrically connected to the first voltage; anda third DC biasing resistor including a first end electrically connected to a cathode of the fourth MOS capacitor and a second end electrically connected to the first voltage; a bias voltage generation circuit configured to bias the plurality of variable capacitor cells including the first variable capacitor cell to control a capacitance of the first variable capacitor array, wherein the bias voltage generation circuit is configured to bias the first variable capacitor cell with the first bias voltage; a first signal swing compensation capacitor electrically connected in parallel with the first pair of anti-series MOS capacitors; and a second signal swing compensation capacitor electrically connected in parallel with the second pair of anti-series MOS capacitors. |
