发明名称 Phase locked loop having fractional VCO modulation
摘要 An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal.
申请公布号 US9484936(B2) 申请公布日期 2016.11.01
申请号 US201514631305 申请日期 2015.02.25
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 Waheed Khurram;Traylor Kevin B.
分类号 H03C1/00;H03C1/12;H03L7/099;H03L7/081;H03B5/12;H03M7/16;H03M3/00;H03C3/09;H03C3/00;H03L7/197 主分类号 H03C1/00
代理机构 代理人
主权项 1. An integrated circuit comprising: a dual port modulator having a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing an integer portion of the high port modulation signal, and a third output for providing a low port signal, the fractional portion of the high port modulation signal generated using a signed single bit signal; a sigma delta modulator to generate a low port modulation signal, the sigma delta modulator having an input for receiving a signal comprising a mix of a target frequency signal with the low port signal, and an output for providing the low port modulation signal; a voltage controlled oscillator (VCO) coupled to the dual port modulator, the VCO having a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal.
地址 Austin TX US