| 摘要 |
<p>A video processing system adds a programmable logic device between a conventional frame buffer (3802) and a conventional digital to analog converter (3811) to provide real time and off-screen processing power to enhance video output capabilities. The system may include a history FIFO (3805) connected to deliver the preceding line to the programmable logic device (3809), allowing operations on a current line, modified as needed by the status of the immediately adjacent vertical pixel. The system may also include inputs for multiple video sources and may include input FIFOs for more ramdom access to portions of the input stream. An alternative form of the system includes a crossbar switch (3905) and multiple memory devices (3906), to allow switching among several possible frame buffer devices. One or more processing units can be added to manipulate a memory which is not the active frame buffer. The processing unit can include a programmable logic device (3911), plus means (3901A) to program the programmable logic device.</p> |
