Trailing or leading zero counter having parallel and combinational logic

摘要

A trailing/leading zero counter includes a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block includes two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also include one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

主权项

1. A zero counter comprising a plurality of hardware logic blocks each arranged to calculate one bit of an output value, the output value corresponding to a number of trailing or leading zeros in an input string, wherein a first of the plurality of hardware logic blocks is arranged to calculate a least significant bit of the output value and comprises:
a low section hardware logic block comprising inputs arranged to receive bits from a first section of the input string including a least significant bit in the input string and one or more logic gates arranged to combine the received bits and generate at least one output; a high section hardware logic block comprising inputs arranged to receive bits from a second section of the input string including a most significant bit in the input string and one or more logic gates arranged to combine the received bits and generate at least one output, wherein the first and second sections of the input string are non-overlapping and comprise all the bits in the input string; and combining logic arranged to combine the outputs of the low and high section hardware logic blocks to generate the least significant bit of the output value, and wherein other hardware logic blocks in the plurality of hardware logic blocks are each arranged to calculate a bit of index i of the output value where i is an integer, each comprising: a) i OR reduction stages arranged in series, a first of the i OR reduction stages arranged to receive the input string and comprising one or more OR gates arranged to combine adjacent bits in the input string to generate an output string and at least one subsequent stage of the i OR reduction stages arranged to receive the output string from a preceding OR reduction stage and comprising one or more OR gates arranged to combine adjacent bits in the received string to generate a further output string; b) a low section hardware logic block comprising inputs arranged to receive bits from a first section of the string output by a last OR reduction stage in the series, the first section including a least significant bit in the received string and one or more logic gates arranged to combine the received bits and generate at least one output; c) a high section hardware logic block comprising inputs arranged to receive bits from a second section of the string output by a last OR reduction stage in the series, the second section including a most significant bit in the received string and one or more logic gates arranged to combine the received bits and generate at least one output, wherein the first and second sections of the received string are non-overlapping and comprise all the bits in the received string; and d) combining logic arranged to combine the output of the two section hardware logic blocks and generate a bit of index i of the output value.