发明名称 ARITHMETIC PROCESSING UNIT AND ITS CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To realize a hierarchical arithmetic processing circuit with less working memory. SOLUTION: The arithmetic processing unit, for executing arithmetic processing for a network hierarchically connected to a plurality of processing nodes for performing an arithmetic operation to input data and generating an arithmetic result, assigns a partial area of memory to each of the plurality of processing nodes, stores the arithmetic result of the arithmetic processing executed by the processing node in an area available for storage in the partial area assigned to the processing node, and sets the area where the arithmetic result referenced by each of the processing nodes connected to the latter part of the processing node as the area available for storage. Whether to execute an arithmetic operation by a processing node designated for arithmetic processing among the processing nodes constituting the network is judged based on the storage state of the arithmetic results in the partial area of the memory allocated to the designated processing node and its preceding node connected. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008310524(A) 申请公布日期 2008.12.25
申请号 JP20070156734 申请日期 2007.06.13
申请人 CANON INC 发明人 YAMAMOTO TAKAHISA;KATO MASAMI;ITO YOSHINORI
分类号 G06N3/063;G06N3/00;G06N3/04 主分类号 G06N3/063
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