Strain enhancement for FinFETs

摘要

An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

主权项

1. An integrated circuit device comprising:
a semiconductor substrate comprising a first portion in a first device region and a second portion in a second device region; a first semiconductor strip in the first device region; a second semiconductor strip in the second device region; a first dielectric liner comprising an edge contacting a sidewall of the first semiconductor strip, wherein the first dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip; and a first Shallow Trench Isolation (STI) region over the first dielectric liner, wherein a sidewall and a bottom surface of the first STI region is in contact with a sidewall and a top surface of the first dielectric liner, respectively, with the top surface being directly underlying the first STI region, and the first STI region comprises:
a sidewall in contact with a sidewall of the first dielectric liner; anda bottom surface comprising a first portion and a second portion, wherein the first portion is in contact with a top surface of the first dielectric liner, and a second portion is in contact with a top surface of the semiconductor substrate.