Fusible and reconfigurable cache architecture

摘要

A reconfigurable cache architecture is provided. In processor design, as the density of on-chip components increases, a quantity and complexity of processing cores will increase as well. In order to take advantage of increased processing capabilities, many applications will take advantage of instruction level parallelism. The reconfigurable cache architecture provides a cache memory that in capable of being configured in a private mode and a fused mode for an associated multi-core processor. In the fused mode, individual cores of the multi-core processor can write and read data from certain cache banks of the cache memory with greater control over address routing. The cache architecture further includes control and configurability of the memory size and associativity of the cache memory itself.

主权项

1. A reconfigurable cache architecture comprising:
a multi-core processor comprising a plurality of cores; a plurality of cache memories configured to store data processed by at least one of the plurality of cores and to provide the stored data to at least one of the plurality of cores upon request; an interconnect network configured to connect at least one core of the plurality of cores to at least one cache memory of the plurality of cache memories; a direct connection network connecting one core of the plurality of cores to one cache memory of the plurality of cache memories; and a system reconfiguration input configured to select between the interconnect network and the direct connection network for each core of the plurality of cores such that the data processed by at least one of the plurality of cores is routed through one of the interconnect network and the direct connection network based on a state of the system reconfiguration input, wherein the interconnect network comprises a combination routing network, and the data processed by at least one of the plurality of cores is routed through the combination routing network based on an address mapping input to the interconnect network, and wherein each individual cache memory of the plurality of cache memories comprises a plurality of cache banks connected in an H-bridge formation with at least one switch connecting the direct connection network to the plurality of cache banks.