CLOCK SIGNAL ADJUSTING CIRCUIT, INTEGRATED CIRCUIT, METHOD FOR CONTROLLING CLOCK SIGNAL ADJUSTING CIRCUIT, CHANNEL ADAPTER DEVICE, DISK ADAPTER DEVICE, AND STORAGE DEVICE CONTROLLER
摘要
<P>PROBLEM TO BE SOLVED: To effectively reduce clock skew. <P>SOLUTION: This clock signal adjusting circuit is provided with: a plurality of phase adjusting circuits which accept the input of first and second clock signals and output third clock signals to control the phase of the first clock signal to be matched with the phase of the second clock signal; and a signal selecting circuit which selects one of the third clock signals to be outputted by those respective phase adjusting circuits and outputs the selected third clock output signal as the second clock signal to each of the phase adjusting circuits. <P>COPYRIGHT: (C)2005,JPO&NCIPI
