Shift register circuit for preventing malfunction due to clock skew and memory device including the same

摘要

A shift register circuit may include a first latch capable of latching an input signal in synchronization with a first clock, a first flip-flop capable of latching the output signal of the first latch in synchronization with a second dock having the same skew as the first clock, a second latch capable of latching the output signal of the first flip-flop in synchronization with a third clock having a different skew from the second clock, and a second flip-flop capable of latching the output signal of the second latch circuit in synchronization with a fourth clock having the same skew as the third clock.

主权项

1. A shift register circuit, comprising:
a first D latch capable of latching an input signal in synchronization with a first clock; a first D flip-flop capable of latching an output signal of the first D latch in synchronization with a second clock having the same skew as the first clock; a second D latch capable of latching an output signal of the first D flip-flop in synchronization with a third clock having a different skew from the second clock; and a second D flip-flop capable of latching an output signal of the second D latch circuit in synchronization with a fourth clock having the same skew as the third clock.