Zero-crossing detection circuit and method for synchronous step-down converter

摘要

In one embodiment, a zero-crossing detection circuit for a synchronous step-down converter, can include: (i) a state determination circuit configured to compare a drain voltage of a synchronous transistor of the synchronous step-down converter against a reference voltage, and to generate a state digital signal indicative of whether a body diode of the synchronous transistor is turned on; (ii) a logic circuit configured to convert the state digital signal into a counting instruction signal; (iii) a plus-minus counter configured to generate a numerical signal in response to the counting instruction signal; (iv) a DAC configured to generate a correction analog signal based on the numerical signal; and (v) a zero-crossing comparator configured to receive the correction analog signal and the drain voltage of the synchronous transistor, and to provide a zero-crossing comparison signal to a driving circuit of the synchronous step-down converter.

主权项

1. A zero-crossing detection circuit for a synchronous step-down converter, the zero-crossing detection circuit comprising:
a) a state determination circuit configured to compare a drain voltage of a synchronous transistor of said synchronous step-down converter against a reference voltage, and to generate a state digital signal indicative of whether a body diode of said synchronous transistor is turned on; b) a logic circuit configured to convert said state digital signal into a counting instruction signal; c) a plus-minus counter configured to generate a numerical signal in response to said counting instruction signal; d) a digital-analog converter configured to generate a correction analog signal based on said numerical signal; e) a zero-crossing comparator configured to receive said correction analog signal and said drain voltage of said synchronous transistor, and to provide a zero-crossing comparison signal to a driving circuit of said synchronous step-down converter; and f) a timing logic circuit configured to receive a first timing signal from said driving circuit, and to generate a second timing signal indicative of an operation time of a comparator, and a third timing signal indicative of an operation time of said logic circuit, wherein said second and third timing signals are respectively provided to said comparator and said logic circuit, and said first timing signal is provided to said plus-minus counter.