PARALLEL SLICE PROCESSOR HAVING A RECIRCULATING LOAD-STORE QUEUE FOR FAST DEALLOCATION OF ISSUE QUEUE ENTRIES

摘要

An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

主权项

1. An execution unit circuit for a processor core, comprising:
an issue queue for receiving a stream of instructions including functional operations and load-store operations; a plurality of internal execution pipelines, including a load-store pipeline for computing effective addresses of load operations and store operations and issuing the load operations and store operations to a cache unit; a recirculation queue for storing entries corresponding to the load operations and the store operations; and control logic for controlling the issue queue, the load-store pipeline and the recirculation queue so that after the load-store pipeline has computed the effective address of a load operation or a store operation, the effective address of the load operation or the store operation is written to the recirculation queue and the load operation or the store operation is removed from the issue queue, the rejected load operation or store operation is subsequently reissued to the cache unit from the recirculation queue.