发明名称 DETERMINING A CELL STATE OF A RESISTIVE MEMORY CELL
摘要 A sensing circuit senses a sensing voltage of a resistive memory cell and outputs a resultant value in response to the sensing voltage which is indicative for the actual cell state. A settling circuit includes a plurality of current mirrors for settling the sensing voltage to a certain target voltage representing one of M programmable cell states. A prebiasing circuit is provided for prebiasing a bitline capacitance of the resistive memory cell such that the sensing voltage is close to the certain target voltage. A resistance circuit includes a plurality of resistors connected in series and coupled in parallel to the resistive memory cell. The resistance circuit is configured to reduce an effective resistance seen by the prebiasing circuit. The settling circuit and the resistance circuit are configured to form a plurality of current-resistor pairs switchable to define a linear range detection currents corresponding to the certain target voltages.
申请公布号 US2016372187(A1) 申请公布日期 2016.12.22
申请号 US201514744013 申请日期 2015.06.18
申请人 International Business Machines Corporation 发明人 Papandreou Nikolaos;Pozidis Charalampos;Stanisavljevic Milos
分类号 G11C13/00;G11C11/56 主分类号 G11C13/00
代理机构 代理人
主权项 1. A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states, the device comprising: a sensing circuit configured to sense a sensing voltage of the resistive memory cell and to output a resultant value in response to the sensing voltage which is indicative for the actual cell state, a settling circuit, including a plurality of current mirrors, configured to settle the sensing voltage to a certain target voltage representing one of the M programmable cell states, a prebiasing circuit configured to pre-bias a bitline capacitance of the resistive memory cell such that the sensing voltage is close to the certain target voltage, and a resistance circuit including a plurality of resistors connected in series and coupled in parallel to the resistive memory cell, wherein the resistance circuit is configured to reduce an effective resistance seen by the prebiasing circuit, wherein the settling circuit and the resistance circuit are configured to form a plurality of current-resistor pairs being switchable to define a linear range of detection currents corresponding to the certain target voltages, each of the plurality of current-resistor pairs including one current mirror and one resistor.
地址 Armonk NY US