Method and an apparatus for coherency control

摘要

The subject matter discloses a method for data coherency; the method comprising receiving an interrupt request for interrupting a CPU; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request notifying a writing instruction of a first data by the one of the plurality of modules to a shared memory; and wherein the shared memory is accessible to the plurality of modules through a shared bus; suspending the interrupt request; validating a completion of an execution of the writing instruction; wherein the validating is performed after the suspending; and resuming the interrupt request after the completion of the execution of the writing is validated, whereby to notify a to the CPU about the completion of the execution of the writing instruction.

主权项

1. A method for data coherency; the method comprising:
receiving by a coherency control module (CCM), an interrupt request for interrupting a central processing unit (CPU), wherein the CPU is coupled to the CCM; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request is for notifying of a writing instruction of a first data by the one of the plurality of modules to a shared memory; andwherein the shared memory is accessible to the plurality of modules through a shared bus;
suspending, by the CCM, the interrupt request by preventing the CPU from receiving the interrupt request; validating, by the CCM, a completion of execution of the writing instruction; and resuming the interrupt request by sending the interrupt request to the CPU.