SEPARATED LOWER SELECT LINE IN 3D NAND ARCHITECTURE

摘要

Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into separate word lines, each defining a block of memory cells. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. String select lines run above the conductive layers, each intersection of a pillar and an string select line defining a respective select gate of the pillar. Bit lines run above the SSLs. Ground select lines run below the conductive layers, each intersection of a pillar and a ground select line defining a respective ground select gate of the pillar. The ground select lines are divided laterally such that the number of ground select lines in each block is greater than 1 but less than the number of string select lines in the block.

主权项

1. A memory device on a substrate, comprising:
a multilevel stack of conductive layers, each of the layers being divided into a plurality of adjacent word lines; a plurality of pillars oriented orthogonally to the conductive layers, each of the pillars comprising a plurality of series-connected memory cells located at cross-points between the pillars and the word lines; a plurality of adjacent string select lines disposed above the conductive layers, each of the string select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a string select line defining a respective string select gate of the pillar; a plurality of parallel bit line conductors disposed above the string select lines, each of the bit line conductors superposing a respective distinct subset of the pillars, each of the pillars underlying one of the bit line conductors; and a plurality of adjacent ground select lines disposed below the conductive layers, each of the ground select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a ground select line defining a respective ground select gate of the pillar, wherein the minimum pitch PGSL in a dimension perpendicular to the string select lines, of the ground select lines in the plurality of adjacent ground select lines, is greater than the minimum pitch PSSL in the dimension perpendicular to the string select lines, of the string select lines in the plurality of adjacent string select lines, but less than the minimum pitch PWL in the dimension perpendicular to the string select lines, of the word lines in the plurality of adjacent word lines.