发明名称 |
Phase detector and associated phase detecting method |
摘要 |
A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals. |
申请公布号 |
US9455725(B2) |
申请公布日期 |
2016.09.27 |
申请号 |
US201514860711 |
申请日期 |
2015.09.22 |
申请人 |
M31 Technology Corporation |
发明人 |
Hung Cheng-Liang;Lin Chun-Cheng;Chang Chih-Hsien;Fan Jiang Chao-Hsin |
分类号 |
H03H11/16;H03L7/081;H03K5/01;H03K5/00 |
主分类号 |
H03H11/16 |
代理机构 |
|
代理人 |
Hsu Winston;Margo Scott |
主权项 |
1. A phase detector, comprising:
a plurality of sampling circuits, for respectively using a plurality of clock signals with different phases to sample at least a data signal so as to generate a plurality of sampling results; a logic circuit, coupled to the plurality of sampling circuits, and configured to generate N phase-leading signals and N phase-lagging signals according to the plurality of sampling results; a plurality of demultiplexers, coupled to the logic circuit, and configured to perform demultiplex operations on the N phase-leading signals and the N phase-lagging signals so as to generate M phase-leading output signals and M phase-lagging output signals, respectively, wherein M is bigger than N, M is a positive integral multiples of N, and frequencies of the M phase-leading output signals and the M phase-lagging output signals are lower than frequencies of the N phase-leading signals and N phase-lagging signals; and a decision circuit, coupled to the plurality of demultiplexers, and configured so as to generate a final phase-leading signal and a final phase-lagging signal according to the M phase-leading output signals and the M phase-lagging output signals. |
地址 |
Hsinchu County TW |