COMMON SOURCE ARCHITECTURE FOR SPLIT GATE MEMORY

摘要

A memory system has an array of split gate non-volatile NVM cells that are in program sectors and the program sectors make up one or more erase sectors. The control gate of cells in a program sector are physically connected. A program/erase circuit programs a selected program sector by applying a programming signal to the control gates of the split gate memory cells of the selected program sector while applying a non-programming signal to the control gates of program sectors not selected for programming, that erases an erase sector comprising a plurality of the program sectors by contemporaneously applying an erase voltage to the control gates of the split gate NVM cells of the erase sector, wherein during the applying the programming signal, the program/erase circuit applies a source voltage to the sources of each of the split gate NVM cells of the erase sector.

主权项

1. A memory system, comprising:
a plurality of split gate non-volatile memory (NVM) cells, wherein:
each split gate NVM cell has a control gate and a source,the plurality of split gate NVM cells are arranged into a plurality of program sectors,each program sector of the plurality of sectors includes a subset of split gate NVM cells of the plurality of split gate NVM cells, andeach program sector has the control gates of its subset of split gate NVM cells physically shorted together; and a program/erase circuit configured to
erase a first erase sector that comprises the plurality of program sectors by
applying an erase voltage to the control gates of each of the split gate NVM cells of the first erase sector, which includes each subset of split gate NVM cells of the plurality of program sectors; andprogram a selected program sector of the plurality of program sectors by simultaneously:
applying a programming signal to the control gates of the split gate NVM cells of the selected program sector,applying a non-programming signal to the control gates of the split gate NVM cells of program sectors of the plurality of program sectors that are not selected for programming, andapplying a source voltage to the sources of each of the split gate NVM cells of the first erase sector.