BITCELL STATE RETENTION

摘要

In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

主权项

1. An apparatus comprising:
an array of magnetoresistive (MRAM) bitcells having first and second rows of MRAM bitcells wherein each bitcell includes a ferromagnetic device having a polarization which in a first bit value storage state is one of parallel and anti-parallel polarization and in a second bit value storage state is the other of parallel and anti-parallel polarization; and control circuitry configured to access a bitcell of the first row wherein said access generates a first magnetic field and wherein said control circuitry is further configured to mitigate a first magnetic field of the first row to maintain a bit value storage state of a bitcell of the second row.