Decoupled selective implementation of entry and exit prediction for power gating processor components

摘要

Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates of reliability of the exit prediction techniques.

主权项

1. A method comprising:
in response to a component of a processing device entering an idle state, selectively implementing by the processing device one or more entry prediction techniques for power gating the component based on first estimates of reliability of the one or more entry prediction techniques, the first estimates of reliability indicating predicted likelihoods that the one or more entry prediction techniques will result in power savings; and selectively implementing by the processing device one or more exit prediction techniques for exiting the power gated state based on second estimates of reliability of the one or more exit prediction techniques, the second estimates of reliability indicating predicted likelihoods that the one or more exit prediction techniques will result in power savings.