发明名称 Compiler having automatic common blocks of memory splitting
摘要 In a computer system having a cache memory and a main memory for storing data, a method for laying out blocks of data to minimize a number of memory transfers between the cache memory and the main memory. Memory layout normally occurs at link time, after all the source files have been compiled. The code is compiled with the assumption that the memory blocks can be optimally placed. The linker then determines whether there has been any memory violations. Memory violations are marked. All marked memory locations are then placed in a layout that satisfies adjacency requirements.
申请公布号 US5848275(A) 申请公布日期 1998.12.08
申请号 US19960688020 申请日期 1996.07.29
申请人 SILICON GRAPHICS, INC. 发明人 MAYDAN, DROR E.;CHAN, SUN C.;DEHNERT, JAMES C.;CARTER, JACK C.
分类号 G06F9/445;G06F9/45;G06F12/08;(IPC1-7):G06F12/06 主分类号 G06F9/445
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