| 摘要 |
PROBLEM TO BE SOLVED: To enable data transfer from a clock domain having a high frequency to a domain having a low frequency and data transfer from a clock domain having a low frequency to a domain having a high frequency, with a small number of elements.SOLUTION: A first flip-flop FF11 receives data on a first clock domain by its input terminal, and receives a first clock signal CLKo by its clock terminal. A first inverter 102 inverts output data DATA on the first flip-flop FF11. A second flip-flop FF12 receives the output data on the first flip-flop FF11 by its input terminal, receives a second clock signal CLKd by its clock terminal, and receives an output of the first inverter by its inverted set terminal RN. A third flip-flop FF13 receives output data DATA_Sync1 on the second flip-flop FF12 by its input terminal, and receives a second clock signal CLKd by its clock terminal.SELECTED DRAWING: Figure 5 |
