发明名称 CLOCK SPURS REDUCTION TECHNIQUE
摘要 Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency. The jitter of the controlled characteristic adjusts a clock harmonic at the radio frequency of the transceiver.
申请公布号 EP3060930(A1) 申请公布日期 2016.08.31
申请号 EP20140815427 申请日期 2014.10.21
申请人 MARVELL WORLD TRADE LTD. 发明人 ROMANO, LUCA
分类号 G01R31/317 主分类号 G01R31/317
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