| 发明名称 | Repair circuit and semiconductor memory device including the same | ||
| 摘要 | A repair circuit includes a normal decoder suitable for decoding partial input addresses of input addresses in response to a first control signal, a comparison unit suitable for comparing the partial input addresses and partial repair addresses of repair addresses in response to a second control signal, and generating a column repair signal when the partial input addresses and the partial repair addresses correspond to each other, and a redundancy decoder suitable for decoding the repair addresses in response to the column repair signal. | ||
| 申请公布号 | US9384859(B2) | 申请公布日期 | 2016.07.05 |
| 申请号 | US201514627875 | 申请日期 | 2015.02.20 |
| 申请人 | SK Hynix Inc. | 发明人 | Yun Tae-Sik |
| 分类号 | G11C7/00;G11C29/00;G11C8/10;G11C29/04;G11C29/50 | 主分类号 | G11C7/00 |
| 代理机构 | IP & T Group LLP | 代理人 | IP & T Group LLP |
| 主权项 | 1. A repair circuit comprising: a normal decoder suitable for decoding partial input addresses of input addresses in response to a first control signal; a comparison unit suitable for comparing the partial input addresses and partial repair addresses of repair addresses in response to a second control signal, and generating a column repair signal if the partial input addresses and the partial repair addresses correspond to each other; and a redundancy decoder suitable for decoding the repair addresses in response to the column repair signal, wherein the first control signal is a double test mode signal, and the second control signal is a signal for a write operation after the double test mode signal is activated. | ||
| 地址 | Gyeonggi-do KR | ||