Modified delta-sigma modulator for phase coherent frequency synthesis applications

摘要

A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency includes a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages. The DSM is operatively coupled to a reference clock configured to generate a cyclical reference signal. The DSM configured to count a number of cycles of the reference signal, to cause, at each cycle of the reference signal, each of the stages of the DSM to accumulate a sum of a previous stage of the DSM, and to multiply each sum by a fractional divide word to produce a multiplier output, thereby causing the DSM to output a sequence of signals that tracks with the reference clock.

主权项

1. A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency, the synthesizer comprising:
a phase detector; and a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages, the DSM and the phase detector each being clocked by a reference clock configured to generate a cyclical reference signal, the DSM configured to:
count a number of the cycles of the reference signal;cause, at each cycle of the reference signal, each subsequent stage of the stages of the DSM to accumulate a sum of a previous stage of the DSM; andmultiply each sum by a fractional divide word to produce a multiplier output, thereby causing the DSM to output a sequence of words that have a deterministic relationship with respect to the reference clock.