Apparatuses and methods for controlling delay circuits during an idle state to reduce degradation of an electrical characteristic

摘要

Delay circuits may be controlled by apparatuses and methods during an idle state to reduce degradation of an electrical characteristic. An example apparatus includes a delay line circuit including a plurality of delay stages, and further includes a delay line control circuit coupled to the delay line circuit. The delay line control circuit is configured to enable delay stages of the plurality of delay stages, and is further configured to control enabled delay stages of the plurality of delay stages to provide a respective output clock signal having a high logic level during an idle state.

主权项

1. An apparatus, comprising:
a delay line circuit including a plurality of delay stages; and a delay line control circuit coupled to the delay line circuit, the delay line control circuit configured to enable delay stages of the plurality of delay stages and further configured to control enabled delay stages of the plurality of delay stages to force a respective output clock signal to a high logic level during an idle state, wherein the delay line control circuit comprises:
a shift register including a plurality of registers, each register of the plurality of registers associated with a respective delay stage of the plurality of delay stages and configured to store information related to enabling or disabling the respective delay stage of the plurality of delay stages; anda plurality of delay stage logic, each delay stage logic of the plurality of delay stage logic coupled to a respective delay stage of the plurality of delay stages and further coupled to a respective register of the plurality of registers, each delay stage logic of the plurality of delay stage logic configured to provide a delay stage enable signal to the respective delay stage of the plurality of delay stages.