Circuits and methods for detecting write operation in resistive random access memory (RRAM) cells

摘要

Circuits and methods for detecting write operation and limiting cell current in resistive random access memory (RRAM or ReRAM) cells are provided. RRAM cells can include a select transistor and a programmable resistor. Current can flow through the programmable resistor responsive to word line voltage VWL applied to the gate of the select transistor and a bit line voltage VBL applied to the source of the select transistor. Responsive to the current, the programmable resistor can change between relatively high and low resistances (“SET”), or between relatively low and high resistances (“RESET”). It can be desirable to accurately characterize the resistance of the programmable resistor, that is, to accurately detect write operations such as SET or RESET. Additionally, it can be undesirable for the current to exceed a certain value (“over-SET”). The present circuits and methods can facilitate detecting write operations or limiting current, or both, in an RRAM cell.

主权项

1. A memory cell, comprising:
a resistive random access memory (RRAM) cell, comprising:
a select transistor; anda programmable resistor, coupled to a source or a drain of the select transistor,wherein the programmable resistor is configured to change between a relatively high resistance and a relatively low resistance responsive to changes in a cell current through the RRAM cell, a dynamic voltage being based on the resistance of the programmable resistor of the RRAM cell; and a write detection circuit coupled to the RRAM cell and configured to receive the dynamic voltage therefrom, the write detection circuit comprising:
a voltage shifting circuit configured to receive the dynamic voltage and a first voltage and to provide as output a second voltage approximately equal to the first voltage divided by approximately two, minus the dynamic voltage; andan inverter comparator circuit comprising a master circuit and a slave circuit,wherein the master circuit is coupled to the voltage shifting circuit and is configured to provide as output a first bias voltage,wherein the slave circuit is coupled to the voltage shifting circuit and to the master circuit and is configured to provide as output a write detection voltage based on the second voltage and the first bias voltage.