发明名称 Vector matrix product accelerator for microprocessor integration
摘要 In at least one example embodiment, a microprocessor circuit is provided that includes a microprocessor core coupled to a data memory via a data memory bus comprising a predetermined integer number of data wires (J); the single-ported data memory configured for storage of vector input elements of an N element vector in a predetermined vector element order and storage of matrix input elements of an M×N matrix comprising M columns of matrix input elements and N rows of matrix input elements; a vector matrix product accelerator comprising a datapath configured for multiplying the N element vector and the matrix to compute an M element result vector, the vector matrix product accelerator comprising: an input/output port interfacing the data memory bus to the vector matrix product accelerator; a plurality of vector input registers for storage respective input vector elements received through the input/output port.
申请公布号 US9384168(B2) 申请公布日期 2016.07.05
申请号 US201313914731 申请日期 2013.06.11
申请人 Analog Devices Global 发明人 Mortensen Mikael
分类号 G06F17/16;G06F9/30;G06F9/38 主分类号 G06F17/16
代理机构 Patent Capital Group 代理人 Patent Capital Group
主权项 1. A vector matrix product accelerator circuit for improving multiplication throughput of a processor, the vector matrix product accelerator circuit comprising: an input/output port interfacing with a data memory bus, wherein the data memory bus couples a processor core to a data memory for storing vector input elements of a vector and matrix input elements of a matrix; vector input registers for storage of vector input elements received through the input/output port; matrix input registers for storage of matrix input elements received through the input/output port; multipliers for producing intermediate multiplication values based on input vector elements and matrix input elements; a sequencer for triggering the multipliers to execute successive multiplication cycles for successive subsets of the vector input elements of the vector and successive subsets of the matrix input elements of the matrix; and an adder circuit for summing the intermediate multiplication values computed through respective multiplier cycles to produce a particular result vector element of a result vector representing a result of multiplying the vector and the matrix.
地址 Hamilton BM