Configurable latch circuit

摘要

In an example implementation, a circuit includes first and second latch circuits. A circuit coupled to the first and second latch circuits is configured to provide a first clock signal to the clock input node of the second latch circuit and provide a second clock signal that is an inversion of the first clock signal to the clock input node of the first latch circuit. The circuit includes a first multiplexer having a first input node coupled to a data output node of the first latch circuit, a second input node coupled to a data input node of the first latch circuit, and an output node coupled to a data input node of the second latch circuit. The circuit also includes a second multiplexer having a first input node coupled to the data output node of the first latch circuit and a second input node coupled to a data output node of the second latch circuit.

主权项

1. A configurable latch circuit, comprising:
first and second latch circuits, each latch circuit having a respective data input node, a respective data output node, and a respective clock input node, wherein each latch circuit is configured to:
set a value of a signal at the respective data output node to a value of a signal at the data input node while the signal at the respective clock input node is set to a first value, andhold the value of the signal at the respective data output node while the signal at the respective clock input node is set to a second value; a circuit coupled to the first and second latch circuits and configured to provide a first clock signal to the clock input node of the second latch circuit and provide a second clock signal that is an inversion of the first clock signal to the clock input node of the first latch circuit; and a first multiplexer having a first input node coupled to the data output node of the first latch circuit, a second input node coupled to the data input node of the first latch circuit, and an output node coupled to the data input node of the second latch circuit; and a second multiplexer having a first input node coupled to the data output node of the first latch circuit and a second input node coupled to the data output node of the second latch circuit.