| 摘要 |
<p>The reliability in a computer system can be maintained by previously excluding potential factors (for example, a correctable error) which may invite a serious failure while preventing degradation of processing capacity performance of a cache memory. The degeneration controller first, for example, increments an error counter provided to count errors for each way. If the count shown by the error counter exceeds a predetermined upper-limit number of times, the degeneration controller writes flag (degeneration information representing that the cache line is degenerated) in a cache tag, with regard to a cache line (for example, Way: n, Index: m) bringing about an error which causes the count to reach the upper-limit number of times.</p> |
