Semiconductor device, manufacturing method of semiconductor device, semiconductor manufacturing and inspecting apparatus, and inspecting apparatus

摘要

A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

主权项

1. A method of manufacturing a semiconductor device comprising the steps of:
forming an insulating layer on a semiconductor substrate; and forming at least one layer of Cu wiring in the insulating layer via a composite layer including a barrier layer and a seed layer on the barrier layer and which is provided between the Cu wiring and the insulating layer, where the barrier layer includes Ta crystal and the seed layer includes an alloy crystal layer of Cu and Al, where 60% or more of all grain boundaries configuring crystals of the Cu wiring are coincidence boundaries of Sigma value 27 or less in at least one cross section of the Cu wiring, and where an orientation of a (111) plane is 93% and an orientation of a (200) plane is 1% in the Cu wiring.