发明名称 Voltage regulating circuit
摘要 In various embodiments, a circuit is provided including a supply terminal, a logic circuit, an inverter and a control transistor which may include a body region, first and second source/drain regions, a gate insulating region having a layer thickness and a gate region. The first source/drain region may be coupled to the supply terminal. The logic circuit may have an internal supply terminal connected to the second source/drain region of the control transistor and a plurality of transistors each having a gate insulating region having a second layer thickness. The inverter input may be coupled to the internal supply terminal of the logic circuit and the output to the gate region of the control transistor. The inverter may include a transistor with a gate insulating region having a third layer thickness substantially equal to the first and second layer thicknesses.
申请公布号 US9377800(B2) 申请公布日期 2016.06.28
申请号 US201514598286 申请日期 2015.01.16
申请人 INFINEON TECHNOLOGIES AG 发明人 Feldtkeller Martin
分类号 G05F1/46;G05F1/56;G05F1/595;G05F1/575 主分类号 G05F1/46
代理机构 代理人
主权项 1. A method for operating a circuit, the method comprising: receiving a supply voltage at a control transistor, wherein the control transistor comprises a body region, a first source/drain region, a second source/drain region, a gate insulating region disposed above the body region and a gate region disposed above the gate insulating region, wherein the first source/drain region receives the supply voltage and wherein the gate insulating region has a first layer thickness; generating by the control transistor, a controlled output voltage at the second source/drain region of the control transistor, wherein a logic circuit is coupled to the second source/drain region of the control transistor, the logic circuit comprising a plurality of transistors, each of the transistors having a gate insulating region of a second layer thickness; and generating by an inverter a control signal, the inverter comprising an inverter input and an inverter output, wherein the inverter input is coupled to the second source/drain region of the control transistor and the inverter output is coupled to the gate of the control transistor, wherein the generated control signal is provided at the inverter output and wherein the inverter comprises at least one transistor with a gate insulating region having a third layer thickness; wherein the first layer thickness, the second layer thickness and the third layer thickness are substantially equal.
地址 Neubiberg DE