Address counter for nonvolatile memory device

摘要

An address counter for a nonvolatile memory device comprising a memory cell array and a page buffer for storing data read from a selected memory array page and to be read therefrom starting from an addressed memory array location during a read sequence and during data input cycles to the device to be written starting from an addressed memory array location during a program sequence, is composed of a cascade of elementary cells. Each cell includes an address counting flip-flop (F/F2) that is updated to the value of every newly counted address bit (ADD) or latches a column address bit value (ADD) input by an external user of the memory device during ALE cycles for addressing said start memory location on the selected page at the rising edge of a clock signal (CK_ADD) generated by an input logic circuitry managing external user's commands, and a carry signal (CARRY) propagation logic circuit along the cascaded elementary cells. Each cell further comprises an additional address loading flip-flop (F/F1) for loading such a column address bit value (LOADADD) input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page at the rising edge of said clock signal (CK_LOAD) during ALE cycles, and logic circuit means for updating the address counting flip flop (F/F2) at the rising edge of said clock signal (CK_ADD) to said address bit value (LOADADD) when is active an internally generated control signal (ENLOAD) that is raised during a read confirm cycle (30h), in a read sequence, and during a first data input cycle (D0), in a program sequence. The new structure prevents glitches and permits to implement multiple internal pipelining buses without employing an adder connected in cascade of the address counter output bus and reducing the possibility of glitches being generated.