发明名称 Memory control device and a delay controller
摘要 A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.
申请公布号 US9396789(B2) 申请公布日期 2016.07.19
申请号 US201514879925 申请日期 2015.10.09
申请人 RICOH COMPANY, LTD. 发明人 Iwasaki Keiichi
分类号 G11C11/4096;G11C11/40;G11C11/406;G11C11/4076;G06F13/42;G11C7/04;G11C7/22 主分类号 G11C11/4096
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P
主权项 1. A memory control device including a delay locked loop circuit, the memory control device comprising: a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory; a first register to store a first DLL value output by the delay locked loop circuit; a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits; and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value, wherein the delay controller calculates the second setting value at n times, where n is a natural number equal to or greater than 1, using the following equation, Bn=(Bn-1/An-1)×An the An-1 is the first DLL value set at n−1 times, the Bn-1 is the first setting value set at the n−1 times, the An is the second DLL value set at n times, and the Bn is the second setting value set at the n times.
地址 Tokyo JP