Selectable-tap equalizer

摘要

A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

主权项

1. An integrated circuit receiver to receive an input signal from a conductive signal path, comprising:
a clock recovery circuit to generate an edge clock; circuitry to generate a data clock and an equalization clock, each of the data clock and the equalization clock being phase-offset relative to the edge clock; a sampling circuit to sample the input signal and generate digital samples according to the data clock; and an equalization circuit to equalize the input signal, in dependence on at least one preceding digital sample, according to the equalization clock; and wherein during a calibration mode,
the integrated circuit receiver is to lock the edge clock against phase adjustment,the equalization circuit is to drive a data pattern onto the conductive signal path according to the equalization clock,the clock recovery circuit is to generate phase adjustments which track transitions in the data pattern relative to the edge clock, andthe circuitry to generate is to adjust the equalization clock responsive to the phase adjustments which track the transitions in the data pattern until the transitions in the data pattern align with the edge clock, to thereby establish the phase-offset of the equalization clock relative to the edge clock for use in a normal operating mode.