| 摘要 |
<P>PROBLEM TO BE SOLVED: To prevent a phase locked loop from being affected by a change of characteristics with the passage of time, the phase locked loop for obtaining an output clock signal phase-locked with an input clock signal. <P>SOLUTION: In the phase-locked loop, the frequency of a clock signal CLK-C output from an oscillator 17 is divided by a DDS 14 to obtain an output clock signal CLK-E, the phase of the output clock signal or a clock signal dividing the frequency of an output signal is compared with that of an input clock signal by a phase comparator 12, the DDS 14 is controlled by a phase comparison output signal, and the output clock signal CLK-E phase-locked with an input clock signal CLK-A is output. The phase locked loop comprises a non-volatile memory 18 which stores a control value inputting the phase comparison output signal of the phase comparator 12 through a loop filter 13 to the DDS 14 as a control value in each passage of a predetermined period, reads the stored control value during a self-traveling mode and inputs it to the DDS 14. <P>COPYRIGHT: (C)2007,JPO&INPIT |
