发明名称 Reducing Visual Artifacts and Reducing Power Consumption in Electrowetting Displays
摘要 Subject matter disclosed herein relates to addressing schemes that reduce visual artifacts and power consumption in electrowetting display devices. The electrowetting display comprises a first substrate and a second substrate opposite to the first substrate, wherein a plurality of pixel regions are defined between the first substrate and the second substrate. The electrowetting display further comprises a first fluid within the pixel regions and a second fluid on the first fluid, wherein the second fluid is immiscible with the first fluid. The electrowetting display also comprises a timing controller that includes a memory. The timing controller is configured to drive the plurality of pixel regions with one or more addressing schemes that control rates of driving the plurality of pixel regions.
申请公布号 US2016189638(A1) 申请公布日期 2016.06.30
申请号 US201414583994 申请日期 2014.12.29
申请人 Amazon Technologies, Inc. 发明人 de Greef Petrus Maria
分类号 G09G3/34;G02B26/00 主分类号 G09G3/34
代理机构 代理人
主权项 1. An electrowetting display comprising: a first substrate and a second substrate opposite to the first substrate; a plurality of pixel walls that intersect to separate a plurality of pixel regions, wherein the plurality of pixel regions is arranged in a grid of rows and columns, wherein each pixel region comprises: a hydrophobic surface on the first substrate;an oil on the hydrophobic surface between the first substrate and the second substrate;a fluid that includes an electrolyte, wherein the fluid is disposed on the electrowetting oil; anda pixel electrode, wherein when a voltage is applied to the pixel region via the pixel electrode in conjunction with a common electrode, a portion of the oil is displaced by the fluid on the hydrophobic surface; a row driver to provide signals to rows of pixel regions and a column driver to provide signals to columns of pixel regions; a timing controller, wherein the timing controller controls the row driver and the column driver to drive pixel regions; and a memory within the timing controller to store image data from a host system, wherein the timing controller controls, based upon the image data stored in the frame memory, the row driver and the column driver to drive the plurality of pixel regions, and wherein the timing controller is further configured to drive the plurality of pixel regions using one or more addressing schemes, wherein the one or more addressing schemes comprise: a first addressing scheme that controls a rate of driving of the plurality of pixel regions independently of a rate of receiving the image data from the host system;a second addressing scheme that limits the rate of driving of the plurality of pixel regions to the rate of receiving the image data from the host system; anda third addressing scheme that reduces the rate of driving of the plurality of pixel regions by skipping images within the image data from the host system.
地址 Seattle WA US